----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:59:42 09/26/2013 
-- Design Name: 
-- Module Name:    mult - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mult is
	port(	clock, load : in STD_LOGIC;
			m, r : in STD_LOGIC_VECTOR(31 downto 0);
			product : out STD_LOGIC_VECTOR(63 downto 0));
end mult;

architecture Behavioral of mult is
	component adder_5op is
		port( a1, a2, a3, a4, a5 : in STD_LOGIC_VECTOR(63 downto 0);
				result : out STD_LOGIC_VECTOR(63 downto 0));
	end component;
	signal pIn : STD_LOGIC_VECTOR(63 downto 0) := X"0000000000000000";
	signal pOut : STD_LOGIC_VECTOR(63 downto 0);
	signal s1, s2, s3, s4 : STD_LOGIC_VECTOR(63 downto 0) := X"0000000000000000";
begin
	adder5Op : adder_5op port map(pIn, s1, s2, s3, s4, pOut);
process(clock)
	variable rReg : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
	variable mReg : STD_LOGIC_VECTOR(63 downto 0) := X"0000000000000000";
begin
	if clock'event and clock = '1' then
		if load = '1' then
			rReg := r;
			mReg := X"00000000" & m;
			pIn <= X"0000000000000000";
			s1 <= X"0000000000000000";
			s2 <= X"0000000000000000";
			s3 <= X"0000000000000000";
			s4 <= X"0000000000000000";
		else
			if rReg /= X"00000000" then
				pIn <= pOut;
				if rReg(0) = '1' then
					s1 <= mReg;
				else 
					s1 <= X"0000000000000000";
				end if;
				mReg := mReg(62 downto 0) & '0';
				
				if rReg(1) = '1' then
					s2 <= mReg;
				else 
					s2 <= X"0000000000000000";
				end if;
				mReg := mReg(62 downto 0) & '0';
				
				if rReg(2) = '1' then
					s3 <= mReg;
				else 
					s3 <= X"0000000000000000";
				end if;
				mReg := mReg(62 downto 0) & '0';
				
				if rReg(3) = '1' then
					s4 <= mReg;
				else 
					s4 <= X"0000000000000000";
				end if;
				mReg := mReg(62 downto 0) & '0';
				
				rReg := "0000" & rReg(31 downto 4);
			end if;
		end if;
		product <= pOut;
	end if;
end process;
end Behavioral;

